FIG. 1 shows a circuit configuration diagram of one example of a conventional oscillation circuit. In FIG. 1, a power source Vdd is connected to one end of a constant current circuit 101, and the sources of p-channel MOS transistors M101 and M103 are connected to the other end thereof. The drain of the MOS transistor 101 is connected to the drain of an n-channel MOS transistor M102, and the source of the MOS transistor M102 is connected to a power source Vss. Further, the drain of the MOS transistor M103 is connected to the drain of an re-channel MOS transistor M104, and the source of the MOS transistor M104 is connected to the power source Vss.
The drains of the MOS transistors M101 and M102 are connected to one end of a capacitor C101, and also, are connected to a non-inverting terminal of a comparator 1027, the other end of the capacitor C101 is connected to the power source Vss. The gates of the MOS transistors M101 and M102 are connected to the Q terminal of a RS flip-flop 104.
Further, the drains of the MOS transistors M103 and M104 are connected to one end of a capacitor C102, and also, are connected to a non-inverting terminal of a comparator 103, the other end of the capacitor C102 is connected to the power source Vss. The gates of the MOS transistors M103 and M104 are connected to the QB terminal of the RS flip-flop 104.
The inverting terminals of the comparators 102 and 103 are connected to one end of a constant voltage circuit 105, a reference voltage Vth is thus applied to the inverting terminals of the comparators 102 and 103, and the other end of the constant voltage circuit 105 is connected to the power source Vss. The current input terminal of the comparator 102 is connected to one end of a constant current circuit 106, thus an operation current is supplied to the comparator 102, and the other end of the constant current circuit 106 is connected to the power source Vss. The comparator 102 generates an output signal that has a high level when the voltage of the capacitor C101 exceeds the reference voltage Vth and has a low level when the voltage is less than or equal to the reference voltage Vth, and supplies the output voltage to the set terminal S of the flip-flop 104.
The current input terminal of the comparator 103 is connected to one end of a constant current circuit 107, thus an operation current is supplied to the comparator 103, and the other end of the constant current circuit 107 is connected to the power source Vss. The comparator 103 generates an output signal that has a high level when the voltage of the capacitor C102 exceeds the reference voltage Vth and has a low level when the voltage is less than or equal to the reference voltage Vth, and supplies the output voltage to the reset terminal R of the flip-flop 104.
The flip-flop 104 has a high level of the Q terminal output and a low level of the QB terminal output when a signal of a high level is supplied to the set terminal S. Further, the flip-flop 104 has a low level of the Q terminal output and a high level of the QB terminal output when a signal of a high level is supplied to the reset terminal R. One or both of the Q terminal output and the QB terminal output of the flip-flop 104 is (are) output as an oscillation signal.
<Operation>
When the Q terminal output of the flip-flop 104 (FIG. 2 (E)) has a low level, the MOS transistor M101 is turned on, the MOS transistor M102 is turned off, the capacitor 101 is thus charged (FIG. 2 (A)), and simultaneously, the QB terminal output of the flip-flop 104 has a high level (FIG. 2 (F)), the MOS transistor M103 is thus turned off, the MOS transistor M104 is turned on, and the capacitor 102 is thus discharged (FIG. 2 (C)). Then, when the voltage of the capacitor 101 has exceeded the reference voltage Vth, the output of the comparator 102 comes to have a high level (FIG. 2 (B)), the flip-flop 104 is set, the Q terminal output thus comes to have a high level and the QB terminal output comes to have a low level.
At this time, the capacitor C101 is discharged as a result of the MOS transistor M101 being turned off and the MOS transistor M102 being turned on, and, simultaneously, the QB terminal output comes to have a low level, and the capacitor C102 is charged as a result of the MOS transistor M103 being turned on and the MOS transistor M104 being turned off. Then, when the voltage of the capacitor 102 has exceeded the reference voltage Vth, the output of the comparator 103 comes to have a high level (FIG. 2 (D)), the flip-flop 104 is reset, the Q terminal output thus comes to have a low level and the QB terminal output comes to have a high level.
A technique is known (for example, see Patent Reference 1) in which an oscillation circuit is formed by using an amplifier generating charging and discharging currents of a capacitor according to rise and fall of first and second input signals; two comparators comparing a terminal voltage Va of the capacitor with an upper limit voltage Vth1 and a lower limit voltage Vth2, respectively; a flip-flop that is reset and set by the respective output signals of the two comparators; and a switch supplying a driving current to one of the two comparators according to a control signal.